As the operation speed of semiconductor integrated circuits or systems including semiconductor integrated circuits increases, it is becoming increasingly important to execute a simulation assuming that semiconductor integrated circuits are mounted on a printed board. In order for a customer (a system manufacturer) to execute such simulation assuming that various semiconductor integrated circuits provided by a plurality of semiconductor device manufacturers are mounted on a common printed board of the customer, a common simulation model is required. For this reason, an I/O buffer information specification (IBIS) model that models package electric characteristics and I/O characteristics of an integrated circuit is internationally standardized (EIA-656-B). Semiconductor device manufacturers providing various semiconductor integrated circuits provide an IBIS model for each of their semiconductor integrated circuits. System manufacturers embedding these semiconductor integrated circuits in a mount board or in a system use these IBIS models provided by the semiconductor device manufacturers. Namely, system manufacturers can execute an IBIS simulation on a mount board or a system on which various semiconductor integrated circuits are mounted.
As transistor-level simulators used for semiconductor integrated circuits, a simulation program with integrated circuit emphasis (SPICE) and SPICE-derived simulators are widely used. In contrast to such transistor-level simulation, an IBIS model treats an I/O buffer connected to an external connection terminal of a semiconductor integrated circuit as a single function, irrespective of circuit configurations or transistor characteristics in the semiconductor integrated circuit. Thus, an IBIS model enables a high-speed simulation. It is said that a simulation based on an IBIS model is ten times faster than a transistor-level simulation based on a SPICE model.
In addition, for semiconductor device manufacturers providing semiconductor integrated circuits, provision of IBIS models is convenient. Since the manufacturers can provide system manufacturers with information necessary for designing mount boards or systems, without disclosing information (trade secret) about the inside of semiconductor integrated circuits, such as characteristics of transistors and detailed configurations of internal circuits.
Thus, manufacturers providing semiconductor integrated circuits, namely, semiconductor integrated circuit suppliers, use transistor-level circuit simulators such as SPICE and simulate AC and DC characteristics of I/O buffers connected to an external I/O terminal of a semiconductor integrated circuit. These suppliers convert these I/O buffer characteristics into an IBIS model and disclose the IBIS model.
Patent Document 1 discloses a method of causing an information processing apparatus to execute an IBIS-description simulation relating to input/output characteristics of a stacked package, in which a plurality of semiconductor chips are stacked. According to Patent Document 1, on-die termination (ODT) values and output buffer device strength values that can be selected per chip are included in advance in a common IBIS description. According to Patent Document 1, users can use a simple method to modify the IBIS description to obtain an IBIS description for a combination of ODT and device strength. In addition, Patent Document 1 discloses that paths from an external connection terminal of the stacked package to the individual chips are written in electrical board description (EBD).
Patent Document 1:
    Japanese Patent Kokai Publication No. JP2007-219930A, which corresponds to US2008/040081A1